soc1: fix uart address decode, connect sout/sin

src/verilog/soc/soc1.v

@@ -34,7 +34,7 @@ module soc1
     localparam ADR_IO_SEL_HI_BIT     = 7;
     localparam ADR_IO_SEL_SIZE       = 4;
     localparam ADR_IO_GPIO           = 4'h0;
-    localparam ADR_IO_UART           = 4'h0;
+    localparam ADR_IO_UART           = 4'h1;
 
     
         // constants
@@ -151,6 +151,8 @@ module soc1
     uart #(
         .DATA_WIDTH(DATA_WIDTH)
     ) uart (
+        .sout(uart_sout),
+        .sin(uart_sin),
         .clk_i(clk),
         .rst_i(rst),
         .cyc_i(cpu_cyc_o),