Commit f544dfe6 authored by Koen Martens's avatar Koen Martens
Browse files

testbench: rename wb_read to wb_check_read

parent 8e2289a7
task wb_check_read(input integer adr, input integer expected, input integer max_wait_cycles = 5);
integer wait_cycles;
string message;
begin
@(posedge clk);
tb_cyc_i = 1'b1; tb_stb_i = 1'b1; tb_adr_i = adr;
wait_cycles = 0;
while (~tb_ack_o) begin
@(posedge clk);
wait_cycles = wait_cycles + 1;
if (wait_cycles == max_wait_cycles) tb_assert(0, "wb_check_read timeout");
end
$sformat(message, "wb_check_read got %0d (0x%2h), expected %0d (0x%2h)", tb_dat_o, tb_dat_o, expected, expected);
tb_assert(tb_dat_o === expected, message);
tb_cyc_i = 1'b0; tb_stb_i = 1'b0;
@(negedge clk);
tb_assert(tb_ack_o === 1'b0, "wb_check_read ack_o de-asserted");
end
endtask
......@@ -53,7 +53,7 @@ module ram_tb();
);
`include "common/testbench_tasks/tb_assert.v"
`include "common/testbench_tasks/wb_read.v"
`include "common/testbench_tasks/wb_check_read.v"
`include "common/testbench_tasks/wb_write.v"
initial begin
......@@ -81,7 +81,7 @@ module ram_tb();
@(posedge clk);
@(posedge clk);
wb_read(3, 8'h42);
wb_check_read(3, 8'h42);
@(posedge clk);
@(posedge clk);
......@@ -94,10 +94,10 @@ module ram_tb();
@(posedge clk);
@(posedge clk);
wb_read(3, 8'hd3);
wb_read(4, 8'had);
wb_read(5, 8'hb4);
wb_read(6, 8'hbe);
wb_check_read(3, 8'hd3);
wb_check_read(4, 8'had);
wb_check_read(5, 8'hb4);
wb_check_read(6, 8'hbe);
@(posedge clk);
......
......@@ -47,7 +47,7 @@ module rom_tb();
);
`include "common/testbench_tasks/tb_assert.v"
`include "common/testbench_tasks/wb_read.v"
`include "common/testbench_tasks/wb_check_read.v"
initial begin
$dumpfile(`VCD_OUTPUT);
......@@ -65,10 +65,10 @@ module rom_tb();
@(posedge clk);
// read 0
wb_read(0, 8'hd3);
wb_read(1, 8'h4d);
wb_read(2, 8'hb4);
wb_read(3, 8'hb3);
wb_check_read(0, 8'hd3);
wb_check_read(1, 8'h4d);
wb_check_read(2, 8'hb4);
wb_check_read(3, 8'hb3);
@(posedge clk);
@(posedge clk);
......
86 20
87 02
80 00
10
87 01
80 55
10
00
86 10
80 23
10
00
09
00
7f
@00000000
84 10 85 01 82 00 E0 54 83 00 E0 5D 84 00 85 50
86 10 87 00 08 10 25 8C 02 88 01 24 27 8C 02 88
01 26 E1 32 8B 02 88 EC E1 3B 8B 02 88 E6 80 03
86 10 87 00 10 28 8B 02 88 FA 84 00 85 47 84 10
85 00 86 00 87 2E 02 47 49 4F 53 20 30 2E 31 00
@00000050
42
......@@ -19,7 +19,7 @@ module top(
parameter DATA_WIDTH = 8;
//wire [DATA_WIDTH-1:0] io_pins = {PIN_7, PIN_6, PIN_5, PIN_4, PIN_3, PIN_2, PIN_1, LED};
wire [DATA_WIDTH-1:0] io_pins = {PIN_7, PIN_6, PIN_5, PIN_4, PIN_3, PIN_2, PIN_1, LED};
wire [DATA_WIDTH-1:0] soc_gpio_in;
wire [DATA_WIDTH-1:0] soc_gpio_out;
......@@ -33,8 +33,8 @@ module top(
.gpio_en(soc_gpio_en)
);
//sb_io io[DATA_WIDTH-1:0] (gpio_in, ~gpio_en, gpio_out, io_pins);
sb_io io[DATA_WIDTH-1:0] (soc_gpio_in, ~soc_gpio_en, soc_gpio_out, io_pins);
/*
sb_io io0 (soc_gpio_in[0], ~soc_gpio_en[0], soc_gpio_out[0], LED);
sb_io io1 (soc_gpio_in[1], ~soc_gpio_en[1], soc_gpio_out[1], PIN_1);
sb_io io2 (soc_gpio_in[2], ~soc_gpio_en[2], soc_gpio_out[2], PIN_2);
......@@ -43,6 +43,6 @@ module top(
sb_io io5 (soc_gpio_in[5], ~soc_gpio_en[5], soc_gpio_out[5], PIN_5);
sb_io io6 (soc_gpio_in[6], ~soc_gpio_en[6], soc_gpio_out[6], PIN_6);
sb_io io7 (soc_gpio_in[7], ~soc_gpio_en[7], soc_gpio_out[7], PIN_7);
*/
endmodule
......@@ -66,7 +66,7 @@ module gpio_tb();
);
`include "common/testbench_tasks/tb_assert.v"
`include "common/testbench_tasks/wb_read.v"
`include "common/testbench_tasks/wb_check_read.v"
`include "common/testbench_tasks/wb_write.v"
initial begin
......@@ -96,19 +96,19 @@ module gpio_tb();
@(posedge clk);
// read input register
wb_read(0, 8'h00);
wb_check_read(0, 8'h00);
@(posedge clk);
tb_gpio_in = 8'h23;
@(posedge clk);
wb_read(0, 8'h23);
wb_check_read(0, 8'h23);
@(posedge clk);
// check hiz register
wb_read(2, 8'hff);
wb_check_read(2, 8'hff);
// configure pins 7-4 as outputs
wb_write(2, 8'h0f);
......@@ -118,7 +118,7 @@ module gpio_tb();
tb_assert(tb_gpio_out === 8'h00, "gpio out is 0");
tb_assert(tb_gpio_en === 8'b00001111, "gpio enable is 0x0f");
wb_read(2, 8'h0f);
wb_check_read(2, 8'h0f);
wb_write(1, 8'b10101010);
......@@ -128,7 +128,7 @@ module gpio_tb();
@(posedge clk);
wb_read(0, 8'b01010101);
wb_check_read(0, 8'b01010101);
$display("passed");
$finish;
......
......@@ -62,7 +62,7 @@ module uart_tb();
);
`include "common/testbench_tasks/tb_assert.v"
`include "common/testbench_tasks/wb_read.v"
`include "common/testbench_tasks/wb_check_read.v"
`include "common/testbench_tasks/wb_write.v"
initial begin
......@@ -101,11 +101,11 @@ module uart_tb();
repeat(200) begin
wb_read(5, 8'h00);
wb_check_read(5, 8'h00);
end
// read input register
//wb_read(0, 8'h00);
//wb_check_read(0, 8'h00);
//tb_assert(tb_uart_out === 8'h00, "uart out is 0");
......
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