Commit e6da09e3 authored by Koen Martens's avatar Koen Martens
Browse files

soc1_tb: add uart, run for 10000 cycles or until halted

parent 75acaa35
......@@ -10,31 +10,44 @@ module soc1_tb();
parameter TB_ADDR_WIDTH = 16;
reg tb_rst;
wire tb_halted;
reg [TB_DATA_WIDTH-1:0] tb_gpio_in;
wire [TB_DATA_WIDTH-1:0] tb_gpio_out;
wire [TB_DATA_WIDTH-1:0] tb_gpio_en;
reg tb_uart_sin;
wire tb_uart_sout;
wire tb_delayed_rst;
wire tb_delay_halted;
wire [TB_DATA_WIDTH-1:0] tb_delayed_gpio_in;
wire [TB_DATA_WIDTH-1:0] tb_delay_gpio_out;
wire [TB_DATA_WIDTH-1:0] tb_delay_gpio_en;
wire tb_delayed_uart_sin;
wire tb_delay_uart_sout;
assign #`TB_IN_DELAY tb_delayed_rst = tb_rst;
assign #`TB_IN_DELAY tb_delayed_gpio_in = tb_gpio_in;
assign #`TB_IN_DELAY tb_delayed_uart_sin = tb_uart_sin;
assign #`TB_IN_DELAY tb_delay_gpio_out = tb_gpio_out;
assign #`TB_IN_DELAY tb_delay_gpio_en = tb_gpio_en;
assign #`TB_IN_DELAY tb_halted = tb_delay_halted;
assign #`TB_IN_DELAY tb_gpio_out = tb_delay_gpio_out;
assign #`TB_IN_DELAY tb_gpio_en = tb_delay_gpio_en;
soc1 UUT (
`include "common/testbench_tasks/tb_assert.v"
integer cycles = 0;
initial begin
$dumpvars(0, soc1_tb);
......@@ -47,8 +60,10 @@ module soc1_tb();
tb_rst = 1'b0;
repeat (1024) begin
cycles = 0;
while((!tb_halted) && (cycles < 100000)) begin
@(posedge clk);
cycles = cycles + 1;
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