Commit ca418d56 authored by Koen Martens's avatar Koen Martens
Browse files

gios: refactor i/o port definitions, use .equ

parent b0ce5251
......@@ -5,9 +5,8 @@ OBJCOPY ?= $(TOOLCHAIN_PREFIX)objcopy
OBJDUMP ?= $(TOOLCHAIN_PREFIX)objdump
OBJS=init.o bootstrap.o serial.o
SOBJS=ports.o
.PRECIOUS: $(OBJS) $(SOBJS) gios.elf
.PRECIOUS: $(OBJS) gios.elf
.PHONY: all clean
......@@ -22,8 +21,8 @@ clean:
%.v: %.elf
$(OBJCOPY) -O verilog $< $@
%.elf: $(OBJS) $(SOBJS) linkrom.scr
$(LD) --script linkrom.scr -R $(SOBJS) -o $@ $(OBJS)
%.elf: $(OBJS) linkrom.scr
$(LD) --script linkrom.scr -o $@ $(OBJS)
$(OBJDUMP) -h gios.elf
%.o: %.S
......
.section io, "e"
.org 0x2010
.global UART_0_RBR
UART_0_RBR:
.org 0x2011
.global UART_0_THR
UART_0_THR:
.org 0x2013
.global UART_0_LCR
UART_0_LCR:
.org 0x2015
.global UART_0_LSR
UART_0_LSR:
; gmcpu8-soc1 port definitions
;
;
.equ UART_0_RBR , 0x2010 ; Receiver Buffer Register, read-only, DLAB=0
.equ UART_0_DLL , 0x2010 ; Divisor Latch (LS), DLAB=1
.equ UART_0_THR , 0x2010 ; Transmitter Holding Register, write-only
.equ UART_0_IER , 0x2011 ; Interrupt Enable Register, DLAB=0
.equ UART_0_DLM , 0x2011 ; Divisor Latch (MS), DLAB=1
.equ UART_0_IIR , 0x2012 ; Interrupt Ident. Register, read-only
.equ UART_0_FCR , 0x2012 ; FIFO Control Register, write-only
.equ UART_0_LCR , 0x2013 ; Line Control Register
.equ UART_0_MCR , 0x2014 ; Modem Control Register
.equ UART_0_LSR , 0x2015 ; Line Status Register
.equ UART_0_MSR , 0x2016 ; Modem Status Register
.equ UART_0_SCR , 0x2017 ; Scratch Register
......@@ -3,6 +3,8 @@
.global uart_send_string
.global uart_flush
.include "ports.inc"
uart_init:
.ldsrc UART_0_LCR
.lddst UART_0_LCR
......@@ -11,11 +13,11 @@ uart_init:
or r0, r1
st r0
.lddst UART_0_RBR ; set DLL
.lddst UART_0_DLL ; set DLL
imm r2, 4
st r2
.lddst UART_0_THR ; set DLM
.lddst UART_0_DLM ; set DLM
imm r2, 0
st r2
......
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