Commit 9ba2341e authored by Koen Martens's avatar Koen Martens
Browse files

cpu: add test-cases for bitwise operations

parent 8939a15e
......@@ -88,14 +88,14 @@ The gmpu8 has an 8-bit wide databus and a 16-bit wide address bus.
- [x] 11100110 x1dddsss - nand rd, rs
- [x] 11100111 x0dddsss - tnor rd, rs
- [x] 11100111 x1dddsss - nor rd, rs
- [ ] 11101000 00dddsss - tshl rd, rs - shift left rd for (rs & 7) bits, shift in 0, update flags, ignore result
- [ ] 11101000 01dddsss - shl rd, rs - shift left rd for (rs & 7) bits, shift in 0, update flags, rd = result
- [ ] 11101000 10dddsss - tshlc rd, rs - shift left rd for (rs & 7) bits, shift in 1, update flags, ignore result
- [ ] 11101000 11dddsss - shlc rd, rs - shift left rd for (rs & 7) bits, shift in 1, update flags, rd = result
- [ ] 11101001 00dddsss - tshr rd, rs - shift right rd for (rs & 7) bits, shift in 0, update flags, ignore result
- [ ] 11101001 01dddsss - shr rd, rs - shift right rd for (rs & 7) bits, shift in 0, update flags, rd = result
- [ ] 11101001 10dddsss - tshrc rd, rs - shift right rd for (rs & 7) bits, shift in 1, update flags, ignore result
- [ ] 11101001 11dddsss - shrc rd, rs - shift right rd for (rs & 7) bits, shift in 1, update flags, rd = result
- [x] 11101000 00dddsss - tshl rd, rs - shift left rd for (rs & 7) bits, shift in 0, update flags, ignore result
- [x] 11101000 01dddsss - shl rd, rs - shift left rd for (rs & 7) bits, shift in 0, update flags, rd = result
- [x] 11101000 10dddsss - tshlc rd, rs - shift left rd for (rs & 7) bits, shift in 1, update flags, ignore result
- [x] 11101000 11dddsss - shlc rd, rs - shift left rd for (rs & 7) bits, shift in 1, update flags, rd = result
- [x] 11101001 00dddsss - tshr rd, rs - shift right rd for (rs & 7) bits, shift in 0, update flags, ignore result
- [x] 11101001 01dddsss - shr rd, rs - shift right rd for (rs & 7) bits, shift in 0, update flags, rd = result
- [x] 11101001 10dddsss - tshrc rd, rs - shift right rd for (rs & 7) bits, shift in 1, update flags, ignore result
- [x] 11101001 11dddsss - shrc rd, rs - shift right rd for (rs & 7) bits, shift in 1, update flags, rd = result
- [ ] 1111???? ???????? - reserved (future three-byte opcode?)
......
......@@ -741,6 +741,22 @@ module cpu_tb();
tb_assert(UUT.sr[UUT.SR_BIT_PARITY] === 'b0, "subc 3 23-42, no parity");
tb_assert(UUT.sr[UUT.SR_BIT_NEGATIVE] === 'b1, "subc 3 23-42, negative");
// tadd
reset();
double_opcode_response('h0000, 'h80, 'h42, "tadd 1 0000: imm r0, 'h42");
double_opcode_response('h0002, 'h81, 'h23, "tadd 1 0002: imm r1, 'h23");
double_opcode_response('h0004, 'he0, 'h01, "tadd 1 0004: add r0, r1");
@(posedge clk);
@(posedge clk);
@(negedge clk);
tb_assert(UUT.r[0] === 'h42, "result tadd 1 42+23 = 42");
tb_assert(UUT.sr[UUT.SR_BIT_ZERO] === 'b0, "tadd 1 42-43, not zero");
tb_assert(UUT.sr[UUT.SR_BIT_CARRY] === 'b0, "tadd 1 42-43, no carry");
tb_assert(UUT.sr[UUT.SR_BIT_OVERFLOW] === 'b0, "tadd 1 42-43, no overflow");
tb_assert(UUT.sr[UUT.SR_BIT_PARITY] === 'b0, "tadd 1 42-43, no parity");
tb_assert(UUT.sr[UUT.SR_BIT_NEGATIVE] === 'b0, "tadd 1 42-43, not negative");
// add
reset();
......@@ -817,6 +833,26 @@ module cpu_tb();
tb_assert(UUT.sr[UUT.SR_BIT_PARITY] === 'b0, "add 5 01+ff, no parity");
tb_assert(UUT.sr[UUT.SR_BIT_NEGATIVE] === 'b0, "add 5 01+ff, not negative");
// taddc
reset();
double_opcode_response('h0000, 'h80, 'h42, "taddc 1 0000: imm r0, 'h42");
double_opcode_response('h0002, 'h81, 'h23, "taddc 1 0002: imm r1, 'h23");
double_opcode_response('h0004, 'he1, 'h08, "taddc 1 0004: cmp r1, r0");
double_opcode_response('h0006, 'h80, 'h42, "taddc 1 0006: imm r0, 'h42");
double_opcode_response('h0008, 'h81, 'h23, "taddc 1 0008: imm r1, 'h23");
double_opcode_response('h000a, 'he0, 'h81, "taddc 1 000a: tadd r0, r1");
@(posedge clk);
@(posedge clk);
@(negedge clk);
tb_assert(UUT.r[0] === 'h42, "result taddc 1 42+23+1 = 42");
tb_assert(UUT.sr[UUT.SR_BIT_ZERO] === 'b0, "taddc 1 42+43+1, not zero");
tb_assert(UUT.sr[UUT.SR_BIT_CARRY] === 'b0, "taddc 1 42+43+1, no carry");
tb_assert(UUT.sr[UUT.SR_BIT_OVERFLOW] === 'b0, "taddc 1 42+43+1, no overflow");
tb_assert(UUT.sr[UUT.SR_BIT_PARITY] === 'b0, "taddc 1 42+43+1, no parity");
tb_assert(UUT.sr[UUT.SR_BIT_NEGATIVE] === 'b0, "taddc 1 42+43+1, not negative");
// addc
reset();
......@@ -856,12 +892,173 @@ module cpu_tb();
tb_assert(UUT.sr[UUT.SR_BIT_PARITY] === 'b1, "addc 2 42+43+1, parity");
tb_assert(UUT.sr[UUT.SR_BIT_NEGATIVE] === 'b0, "addc 2 42+43+1, not negative");
// tneg
reset();
double_opcode_response('h0000, 'h80, 'b10101100, "tneg 1 0000: imm r0, 'b10101100");
double_opcode_response('h0002, 'he2, 'h00, "tneg 1 0002: tneg r0");
@(posedge clk);
@(posedge clk);
@(negedge clk);
tb_assert(UUT.r[0] === 'b10101100, "result tneg 1 'b10101100 = 'b10101100");
tb_assert(UUT.sr[UUT.SR_BIT_ZERO] === 'b0, "tneg 1 'b10101100, not zero");
tb_assert(UUT.sr[UUT.SR_BIT_CARRY] === 'b0, "tneg 1 'b10101100, no carry");
tb_assert(UUT.sr[UUT.SR_BIT_OVERFLOW] === 'b0, "tneg 1 'b10101100, no overflow");
tb_assert(UUT.sr[UUT.SR_BIT_PARITY] === 'b0, "tneg 1 'b10101100, no parity");
tb_assert(UUT.sr[UUT.SR_BIT_NEGATIVE] === 'b0, "tneg 1 'b10101100, not negative");
reset();
double_opcode_response('h0000, 'h80, 'b01010010, "tneg 2 0000: imm r0, 'b01010010");
double_opcode_response('h0002, 'he2, 'h00, "tneg 2 0002: tneg r0");
@(posedge clk);
@(posedge clk);
@(negedge clk);
tb_assert(UUT.r[0] === 'b01010010, "result tneg 2 'b01010010 = 'b01010010");
tb_assert(UUT.sr[UUT.SR_BIT_ZERO] === 'b0, "tneg 2 'b01010010, not zero");
tb_assert(UUT.sr[UUT.SR_BIT_CARRY] === 'b0, "tneg 2 'b01010010, no carry");
tb_assert(UUT.sr[UUT.SR_BIT_OVERFLOW] === 'b0, "tneg 2 'b01010010, no overflow");
tb_assert(UUT.sr[UUT.SR_BIT_PARITY] === 'b1, "tneg 2 'b01010010, parity");
tb_assert(UUT.sr[UUT.SR_BIT_NEGATIVE] === 'b1, "tneg 2 'b01010010, negative");
reset();
double_opcode_response('h0000, 'h80, 'b11111111, "tneg 3 0000: imm r0, 'b11111111");
double_opcode_response('h0002, 'he2, 'h00, "tneg 3 0002: tneg r0");
@(posedge clk);
@(posedge clk);
@(negedge clk);
tb_assert(UUT.r[0] === 'b11111111, "result tneg 3 'b11111111 = 'b11111111");
tb_assert(UUT.sr[UUT.SR_BIT_ZERO] === 'b1, "tneg 3 'b11111111, zero");
tb_assert(UUT.sr[UUT.SR_BIT_CARRY] === 'b0, "tneg 3 'b11111111, no carry");
tb_assert(UUT.sr[UUT.SR_BIT_OVERFLOW] === 'b0, "tneg 3 'b11111111, no overflow");
tb_assert(UUT.sr[UUT.SR_BIT_PARITY] === 'b0, "tneg 3 'b11111111, no parity");
tb_assert(UUT.sr[UUT.SR_BIT_NEGATIVE] === 'b0, "tneg 3 'b11111111, not negative");
// neg2
reset();
double_opcode_response('h0000, 'h80, 'b10101100, "neg2 1 0000: imm r0, 'b10101100");
double_opcode_response('h0002, 'he2, 'h40, "neg2 1 0002: neg2 r0");
@(posedge clk);
@(posedge clk);
@(negedge clk);
tb_assert(UUT.r[0] === 'b01010011, "result neg2 1 'b10101100 = 'b10101100");
tb_assert(UUT.sr[UUT.SR_BIT_ZERO] === 'b0, "neg2 1 'b10101100, not zero");
tb_assert(UUT.sr[UUT.SR_BIT_CARRY] === 'b0, "neg2 1 'b10101100, no carry");
tb_assert(UUT.sr[UUT.SR_BIT_OVERFLOW] === 'b0, "neg2 1 'b10101100, no overflow");
tb_assert(UUT.sr[UUT.SR_BIT_PARITY] === 'b0, "neg2 1 'b10101100, no parity");
tb_assert(UUT.sr[UUT.SR_BIT_NEGATIVE] === 'b0, "neg2 1 'b10101100, not negative");
reset();
double_opcode_response('h0000, 'h80, 'b01010010, "neg 2 0000: imm r0, 'b01010010");
double_opcode_response('h0002, 'he2, 'hc0, "neg 2 0002: neg r0");
@(posedge clk);
@(posedge clk);
@(negedge clk);
tb_assert(UUT.r[0] === 'b10101101, "result neg2 2 'b01010010 = 'b10101101");
tb_assert(UUT.sr[UUT.SR_BIT_ZERO] === 'b0, "neg2 2 'b01010010, not zero");
tb_assert(UUT.sr[UUT.SR_BIT_CARRY] === 'b0, "neg2 2 'b01010010, no carry");
tb_assert(UUT.sr[UUT.SR_BIT_OVERFLOW] === 'b0, "neg2 2 'b01010010, no overflow");
tb_assert(UUT.sr[UUT.SR_BIT_PARITY] === 'b1, "neg2 2 'b01010010, parity");
tb_assert(UUT.sr[UUT.SR_BIT_NEGATIVE] === 'b1, "neg2 2 'b01010010, negative");
reset();
double_opcode_response('h0000, 'h80, 'b11111111, "neg2 3 0000: imm r0, 'b11111111");
double_opcode_response('h0002, 'he2, 'h40, "neg2 3 0002: tneg r0");
@(posedge clk);
@(posedge clk);
@(negedge clk);
tb_assert(UUT.r[0] === 'b00000000, "result neg2 3 'b11111111 = 'b00000000");
tb_assert(UUT.sr[UUT.SR_BIT_ZERO] === 'b1, "neg2 3 'b11111111, zero");
tb_assert(UUT.sr[UUT.SR_BIT_CARRY] === 'b0, "neg2 3 'b11111111, no carry");
tb_assert(UUT.sr[UUT.SR_BIT_OVERFLOW] === 'b0, "neg2 3 'b11111111, no overflow");
tb_assert(UUT.sr[UUT.SR_BIT_PARITY] === 'b0, "neg2 3 'b11111111, no parity");
tb_assert(UUT.sr[UUT.SR_BIT_NEGATIVE] === 'b0, "neg2 3 'b11111111, not negative");
// and
reset();
double_opcode_response('h0000, 'h80, 'b10101100, "and 1 0000: imm r0, 'b10101100");
double_opcode_response('h0002, 'h81, 'b11001010, "and 1 0002: imm r1, 'b11001010");
double_opcode_response('h0004, 'he3, 'h41, "and 1 0004: and r0, r1");
@(posedge clk);
@(posedge clk);
@(negedge clk);
tb_assert(UUT.r[0] === 'b10001000, "result and 1 = 'b10001000");
tb_assert(UUT.sr[UUT.SR_BIT_ZERO] === 'b0, "and 1, not zero");
tb_assert(UUT.sr[UUT.SR_BIT_CARRY] === 'b0, "and 1, no carry");
tb_assert(UUT.sr[UUT.SR_BIT_OVERFLOW] === 'b0, "and 1, no overflow");
tb_assert(UUT.sr[UUT.SR_BIT_PARITY] === 'b0, "and 1, no parity");
tb_assert(UUT.sr[UUT.SR_BIT_NEGATIVE] === 'b1, "and 1, negative");
// or
reset();
double_opcode_response('h0000, 'h80, 'b10101100, "or 1 0000: imm r0, 'b10101100");
double_opcode_response('h0002, 'h81, 'b11001010, "or 1 0002: imm r1, 'b11001010");
double_opcode_response('h0004, 'he4, 'hc1, "or 1 0004: or r0, r1");
@(posedge clk);
@(posedge clk);
@(negedge clk);
tb_assert(UUT.r[0] === 'b11101110, "result or 1 = 'b11101110");
tb_assert(UUT.sr[UUT.SR_BIT_ZERO] === 'b0, "or 1, not zero");
tb_assert(UUT.sr[UUT.SR_BIT_CARRY] === 'b0, "or 1, no carry");
tb_assert(UUT.sr[UUT.SR_BIT_OVERFLOW] === 'b0, "or 1, no overflow");
tb_assert(UUT.sr[UUT.SR_BIT_PARITY] === 'b0, "or 1, no parity");
tb_assert(UUT.sr[UUT.SR_BIT_NEGATIVE] === 'b1, "or 1, negative");
// xor
reset();
double_opcode_response('h0000, 'h80, 'b10101100, "xor 1 0000: imm r0, 'b10101100");
double_opcode_response('h0002, 'h81, 'b11001010, "xor 1 0002: imm r1, 'b11001010");
double_opcode_response('h0004, 'he5, 'h41, "xor 1 0004: xor r0, r1");
@(posedge clk);
@(posedge clk);
@(negedge clk);
tb_assert(UUT.r[0] === 'b01100110, "result xor 1 = 'b01100110");
tb_assert(UUT.sr[UUT.SR_BIT_ZERO] === 'b0, "xor 1, not zero");
tb_assert(UUT.sr[UUT.SR_BIT_CARRY] === 'b0, "xor 1, no carry");
tb_assert(UUT.sr[UUT.SR_BIT_OVERFLOW] === 'b0, "xor 1, no overflow");
tb_assert(UUT.sr[UUT.SR_BIT_PARITY] === 'b0, "xor 1, no parity");
tb_assert(UUT.sr[UUT.SR_BIT_NEGATIVE] === 'b0, "xor 1, not negative");
// nand
reset();
double_opcode_response('h0000, 'h85, 'b10101100, "nand 1 0000: imm r5, 'b10101100");
double_opcode_response('h0002, 'h86, 'b11001010, "nand 1 0002: imm r6, 'b11001010");
double_opcode_response('h0004, 'he6, 'h6e, "nand 1 0004: nand r5, r6");
@(posedge clk);
@(posedge clk);
@(negedge clk);
tb_assert(UUT.r[5] === 'b01110111, "result nand 1 = 'b01110111");
tb_assert(UUT.sr[UUT.SR_BIT_ZERO] === 'b0, "nand 1, not zero");
tb_assert(UUT.sr[UUT.SR_BIT_CARRY] === 'b0, "nand 1, no carry");
tb_assert(UUT.sr[UUT.SR_BIT_OVERFLOW] === 'b0, "nand 1, no overflow");
tb_assert(UUT.sr[UUT.SR_BIT_PARITY] === 'b0, "nand 1, no parity");
tb_assert(UUT.sr[UUT.SR_BIT_NEGATIVE] === 'b0, "nand 1, not negative");
// nor
reset();
double_opcode_response('h0000, 'h85, 'b10101100, "nor 1 0000: imm r5, 'b10101100");
double_opcode_response('h0002, 'h86, 'b11001010, "nor 1 0002: imm r6, 'b11001010");
double_opcode_response('h0004, 'he7, 'h6e, "nor 1 0004: nor r5, r6");
@(posedge clk);
@(posedge clk);
@(negedge clk);
tb_assert(UUT.r[5] === 'b00010001, "result nor 1 = 'b00010001");
tb_assert(UUT.sr[UUT.SR_BIT_ZERO] === 'b0, "nor 1, not zero");
tb_assert(UUT.sr[UUT.SR_BIT_CARRY] === 'b0, "nor 1, no carry");
tb_assert(UUT.sr[UUT.SR_BIT_OVERFLOW] === 'b0, "nor 1, no overflow");
tb_assert(UUT.sr[UUT.SR_BIT_PARITY] === 'b0, "nor 1, no parity");
tb_assert(UUT.sr[UUT.SR_BIT_NEGATIVE] === 'b0, "nor 1, not negative");
@(posedge clk);
@(posedge clk);
@(posedge clk);
......
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