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Commit 28f3e4ca authored by Koen Martens's avatar Koen Martens
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uart: make transmit_tb more dry

parent bcba8085
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src/verilog/wishbone/uart/transmit_tb.v
View file @ 28f3e4ca
......@@ -47,62 +47,29 @@ module transmit_tb();
task verify_sout(
input [TB_DATA_WIDTH-1:0] expected,
input string message = ""
input string message = "",
input integer start_skip = 0,
input integer stop_skip = 0
);
integer bit_index;
string formatted;
begin
repeat(32) begin
repeat(32-start_skip) begin
@(posedge clk);
tb_assert(tb_sout === 1'b0, {message, ", start bit (0)"});
tb_assert(tb_data_latched_o===1'b0, {message, ", start, data_latched_o deasserted"});
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout === expected[0], {message, ", bit0 (1)"});
tb_assert(tb_data_latched_o===1'b0, {message, ", bit 0, data_latched_o deasserted"});
end
expected = expected >> 1;
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout === expected[0], {message, ", bit1 (1)"});
tb_assert(tb_data_latched_o===1'b0, {message, ", bit 1, data_latched_o deasserted"});
end
expected = expected >> 1;
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout === expected[0], {message, ", bit2 (0)"});
tb_assert(tb_data_latched_o===1'b0, {message, ", bit 2, data_latched_o deasserted"});
end
expected = expected >> 1;
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout === expected[0], {message, ", bit3 (1)"});
tb_assert(tb_data_latched_o===1'b0, {message, ", bit 3, data_latched_o deasserted"});
end
expected = expected >> 1;
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout === expected[0], {message, ", bit4 (0)"});
tb_assert(tb_data_latched_o===1'b0, {message, ", bit 4, data_latched_o deasserted"});
end
expected = expected >> 1;
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout === expected[0], {message, ", bit5 (0)"});
tb_assert(tb_data_latched_o===1'b0, {message, ", bit 5, data_latched_o deasserted"});
end
expected = expected >> 1;
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout === expected[0], {message, ", bit6 (1)"});
tb_assert(tb_data_latched_o===1'b0, {message, ", bit 6, data_latched_o deasserted"});
end
expected = expected >> 1;
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout === expected[0], {message, ", bit7 (0)"});
tb_assert(tb_data_latched_o===1'b0, {message, ", bit 7, data_latched_o deasserted"});
bit_index = 0;
repeat(8) begin
repeat(32) begin
@(posedge clk);
$sformat(formatted, {message, ", bit %0d (%b)"}, bit_index, expected[bit_index]);
tb_assert(tb_sout === expected[bit_index], {formatted, ", sout correct"});
tb_assert(tb_data_latched_o===1'b0, {formatted, ", data_latched_o deasserted"});
end
bit_index += 1;
end
repeat(31) begin
repeat(32-stop_skip) begin
@(posedge clk);
tb_assert(tb_sout === 1'b1, {message, ", stop bit (1)"});
tb_assert(tb_data_latched_o===1'b0, {message, ", stop bit, data_latched_o deasserted"});
......@@ -116,7 +83,8 @@ module transmit_tb();
$dumpfile(`VCD_OUTPUT);
$dumpvars(0, transmit_tb);
tb_rst_i = 1'b1; tb_clk_divisor_i = 2; tb_data_i = 'h4b; tb_data_ready_i = 1'b0;
// reset
tb_rst_i = 1'b1; tb_clk_divisor_i = 2; tb_data_i = 'h00; tb_data_ready_i = 1'b0;
@(posedge clk);
......@@ -128,6 +96,8 @@ module transmit_tb();
@(posedge clk);
@(posedge clk);
// byte 1
tb_data_i = 'h4b;
tb_data_ready_i = 1'b1;
@(posedge clk);
tb_data_ready_i = 1'b0;
......@@ -140,60 +110,8 @@ module transmit_tb();
tb_data_i = 'b10110100; tb_data_ready_i = 1'b1;
// byte 1
verify_sout('h4b, "byte 1");
/*
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b0, "byte 1, start bit (0)");
tb_assert(tb_data_latched_o==1'b0, "byte 1, start, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b1, "byte 1, bit0 (1)");
tb_assert(tb_data_latched_o==1'b0, "byte 1, bit 0, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b1, "byte 1, bit1 (1)");
tb_assert(tb_data_latched_o==1'b0, "byte 1, bit 1, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b0, "byte 1, bit2 (0)");
tb_assert(tb_data_latched_o==1'b0, "byte 1, bit 2, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b1, "byte 1, bit3 (1)");
tb_assert(tb_data_latched_o==1'b0, "byte 1, bit 3, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b0, "byte 1, bit4 (0)");
tb_assert(tb_data_latched_o==1'b0, "byte 1, bit 4, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b0, "byte 1, bit5 (0)");
tb_assert(tb_data_latched_o==1'b0, "byte 1, bit 5, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b1, "byte 1, bit6 (1)");
tb_assert(tb_data_latched_o==1'b0, "byte 1, bit 6, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b0, "byte 1, bit7 (0)");
tb_assert(tb_data_latched_o==1'b0, "byte 1, bit 7, data_latched_o deasserted");
end
repeat(31) begin
@(posedge clk);
tb_assert(tb_sout == 1'b1, "byte 1, stop bit (1)");
tb_assert(tb_data_latched_o==1'b0, "byte 1, stop bit, data_latched_o deasserted");
end
*/
verify_sout('h4b, "byte 1", 0, 1);
@(posedge clk);
tb_assert(tb_sout == 1'b1, "byte 1, stop bit (1) last period");
tb_assert(tb_data_latched_o==1'b1, "byte 1, data_latched_o asserted for byte 2");
......@@ -204,56 +122,7 @@ module transmit_tb();
// byte 2 ('b10110100)
tb_assert(tb_data_latched_o==1'b0, "data_latched_o deasserted after clock cycle for byte 2");
repeat(31) begin
@(posedge clk);
tb_assert(tb_sout == 1'b0, "byte 2, start bit (0)");
tb_assert(tb_data_latched_o==1'b0, "byte 2, start, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b0, "byte 2, bit0 (0)");
tb_assert(tb_data_latched_o==1'b0, "byte 2, bit 0, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b0, "byte 2, bit1 (0)");
tb_assert(tb_data_latched_o==1'b0, "byte 2, bit 1, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b1, "byte 2, bit2 (1)");
tb_assert(tb_data_latched_o==1'b0, "byte 2, bit 2, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b0, "byte 2, bit3 (0)");
tb_assert(tb_data_latched_o==1'b0, "byte 2, bit 3, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b1, "byte 2, bit4 (1)");
tb_assert(tb_data_latched_o==1'b0, "byte 2, bit 4, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b1, "byte 2, bit5 (1)");
tb_assert(tb_data_latched_o==1'b0, "byte 2, bit 5, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b0, "byte 2, bit6 (0)");
tb_assert(tb_data_latched_o==1'b0, "byte 2, bit 6, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b1, "byte 2, bit7 (1)");
tb_assert(tb_data_latched_o==1'b0, "byte 2, bit 7, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b1, "byte 2, stop bit (1)");
tb_assert(tb_data_latched_o==1'b0, "byte 2, stop bit, data_latched_o deasserted");
end
verify_sout('b10110100, "byte 2", 1, 0);
repeat(10) @(posedge clk);
......@@ -269,58 +138,9 @@ module transmit_tb();
@(negedge clk);
tb_assert(tb_data_latched_o==1'b0, "byte 3, data_latched_o deasserted after clock cycle");
// byte 3
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b0, "byte 3, start bit (0)");
tb_assert(tb_data_latched_o==1'b0, "byte 3, start, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b0, "byte 3, bit0 (0)");
tb_assert(tb_data_latched_o==1'b0, "byte 3, bit 0, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b1, "byte 3, bit1 (1)");
tb_assert(tb_data_latched_o==1'b0, "byte 3, bit 1, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b0, "byte 3, bit2 (0)");
tb_assert(tb_data_latched_o==1'b0, "byte 3, bit 2, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b1, "byte 3, bit3 (1)");
tb_assert(tb_data_latched_o==1'b0, "byte 3, bit 3, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b0, "byte 3, bit4 (0)");
tb_assert(tb_data_latched_o==1'b0, "byte 3, bit 4, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b1, "byte 3, bit5 (1)");
tb_assert(tb_data_latched_o==1'b0, "byte 3, bit 5, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b0, "byte 3, bit6 (0)");
tb_assert(tb_data_latched_o==1'b0, "byte 3, bit 6, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b1, "byte 3, bit7 (1)");
tb_assert(tb_data_latched_o==1'b0, "byte 3, bit 7, data_latched_o deasserted");
end
repeat(32) begin
@(posedge clk);
tb_assert(tb_sout == 1'b1, "byte 3, stop bit (1)");
tb_assert(tb_data_latched_o==1'b0, "byte 3, stop bit, data_latched_o deasserted");
end
verify_sout('b10101010, "byte 2", 0, 0);
// idle
repeat(10) begin
@(posedge clk);
tb_assert(tb_sout == 1'b1, "idle (1)");
......
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